The formation of trenches using various masking and etching techniques is well-known in the prior art. Similarly, the refilling of trenches for isolation and device forming purposes is also well-known. An article entitled "Self-Aligning Multi-Depth Trenches" in the IBM Technical Disclosure Bulletin, Vol. 28, No. 3, August 1985, page 1235 shows the formation of orthogonally disposed deep and shallow trenches which can be refilled with a suitable material. In the article, the trenches are used to obtain both deep and shallow isolation. The isolated epitaxial areas are subsequently utilized to form bipolar devices.
U.S. Pat. No. 4,520,553, filed Jan. 16, 1984, shows a semiconductor device with a deep grid accessible via the surface having a silicon substrate and comprising U-shaped grooves. The upper parts of the sidewalls of the grooves are insulated by a silicon layer and the lower parts of the grooves connect up with heavily doped zones. Polycrystalline silicon provides ohmic contact between selected positions on the upper face of the transistor and the grid layer. The reference basically shows the formation of grooves, filling with polysilicon and outdiffusing to provide dopant regions at the bottom of the grooves. While there are interconnections between rows of devices, there are no connections between devices in an orthogonal direction. Differential etching is not contemplated in the method of this reference.
U.S. Pat. No. 4,510,016, filed Dec. 9, 1982, shows a submicron structure including a plurality of fingers which are thinned down by the repeated oxidation and stripping of the walls of a U-shaped groove. In this reference a portion of each of the devices is formed by etching grooves in a semiconductor. The regions between the grooves are left open so that in a subsequent metallization step both emitter and self-aligned Schottky barrier contacts can be formed. The spacing between the devices is in only one direction.
An abstract of Japanese Patent No. 59-19366, filed Jan. 31, 1984, shows a vertical field effect transistor memory cell disposed within an isolation region which is itself formed in a semiconductor substrate counterelectrode. In this arrangement, a groove is formed in the semiconductor substrate which is refilled with polycrystalline silicon. After planarizing, layers of semiconductor from which a channel region and source of an FET device are to be formed are disposed atop the polished polycrystalline. To the extent that the layers formed on the polycrystalline semiconductor are themselves polycrystalline in character, these layers must be rendered single crystal by a technique called laser recrystallization. Further masking and etching steps form a pedestal of these layers which are then surrounded with insulating material up to the level of the polycrystalline in the mesa. A polycrystalline silicon gate is then disposed in insulated spaced relationship with the channel region. The gate is then electrically insulated and metallization applied to the single crystal semiconductor source region to form bitlines which are disposed orthogonal to the polycrystalline gate which forms a wordline for a column of similar memory cells. Thus, while a vertical device is formed, its structure and method of fabrication are such that techniques like laser recrystallization must be invoked providing, at best, epitaxial regions of questionable quality for the transfer device of each memory cell. In the technique just described, a straightforward etch and refill technique is involved without invoking the differential etch technique of the present application.
It is, therefore, an object of the present invention to provide an ultra dense DRAM memory array wherein each memory cell is made of a vertical single crystal, device regions wherein the single crystal material requires no special technique to form it other than epitaxial disposition and etching.
Another object is to provide a method for forming an ultra dense DRAM memory array wherein a differential etching step is utilized to simultaneously etch two different materials at different rates such that transistor device regions are formed and the height of insulating conduits to be formed subsequently is predetermined.
Still another object is to provide an ultra dense DRAM memory array wherein the width of the active device region is defined by a spacer smaller than the lithographic limit.
Yet another object is to provide an ultra dense memory array wherein pairs of wordlines are formed in insulating conduits portions of which are formed from isolation regions of reduced height and other portions of which are formed from oxidized portions of a common conductive counterelectrode.